1. Field of the Invention
The present invention provides a method for monitoring quality of an insulation layer, and more particularly, relates to a method for quickly monitoring the stress-induced degradation of an insulation layer in different structures with wafer acceptance testing (WAT) equipment.
2. Description of the Prior Art
In today's electronics industry, semiconductor devices make extensive use of the unique characteristics of semiconductor materials. Most recently, transistors known as metal-oxide-semiconductor (MOS) transistors have been created that consume less power and can be highly integrated. These tiny transistors have been widely used in various electronic devices and circuits. Non-volatile memory, such as the frequently seen flash ROM or other electrically erasable programmable ROM (EEPROM), is one kind of memory. Once information or data is stored into the non-volatile memory, the stored information or data will not disappear due to the interruption of power supply. The non-volatile memory thus is able to retain data and becomes a key component in the electronics industry. Besides MOS transistors and non-volatile memories, many different devices or structures, such as resistors, capacitors, inductors, interconnection structures, etc., are formed on the semiconductor wafers to constitute different circuits.
In order to fabricate satisfied semiconductor products, qualities of the above-mentioned devices should be well controlled. When considering the qualities of MOS transistors, non-volatile memories, capacitors, and interconnect structures, the qualities of the insulation layers, having various compositions, in these devices or structure become important issues. Therefore, it is very important to monitor qualities of the insulation layers in these devices on the production line.
Actually, the stress-induced degradation of the insulation layer tends to occur, no matter what kind of insulation layer is. In the following, a flash ROM is taken as an example, to illustrate the stress-induced degradation phenomenon. Flash ROM, regarded as one kind of non-volatile memory, usually utilizes a floating gate composed of polysilicon or metal for storing charges. Therefore, an extra gate exists aside from a typical control gate when compared with MOS. Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are schematic diagrams of writing and erasing a flash ROM cell 10. As shown in FIG. 1, the flash ROM cell 10 is fabricated on a semiconductor substrate 12. The flash ROM cell 10 comprises a floating gate 14 and a control gate 16. Two N-type doping areas 18 are set in the semiconductor substrate 12 at two sides of the floating gate 14 and the control gate 16, and a channel 22 is defined between the two N-type doping areas 18.
When writing to the cell, hot electrons tunnel through a thin silicon dioxide layer (not shown) beneath the floating gate 14, enter the floating gate 14, and are trapped in the floating gate 14. Storing negative charges in the floating gate 14 represents storing a data “1” in the flash ROM cell 10, as opposed to storing a “0”. To electrically erase a memory state of the flash ROM cell 10, adequate negative voltage must be applied to the control gate 16 of the flash ROM cell 10. The electrons trapped in the floating gate 14 tunnel through the thin silicon dioxide layer (not shown) beneath the floating gate 14 again, and escape from the floating gate 14. The data stored in the flash ROM cell 10 is erased, the state before storing information is recovered, and new information can be written into the flash ROM cell 10.
However, when electrons or holes flow through the channel, they are apt to be affected by an electric field and gain energy to become a so-called hot carrier. These energetic hot carriers will alter their original path and be injected into the oxide layer to become oxide-trapped charges (Not), to drift through the oxide layer and cause leakage current flowing through the gate (IG), to create interface-trapped charges (Dit), and to generate photons. Both the oxide-trapped charges and the interface-trapped charges cause a threshold voltage shift and mobility degradation. The voltage applied to the gate creates a voltage difference (Vox) traverse the oxide layer. An effect frequently observed in electric field stressed oxides is a gate oxide current increase, referred to as stress-induced leakage current (SILC).
The most likely mechanism causing this current increase is trap-assisted tunneling where electrons or holes tunnel from the substrate to the gate through intermediate oxide traps. These traps are generated by the high-field stress and they facilitate electrons or holes tunneling to enhance the current. The intermediate trapped charges comprise not only the previous mentioned oxide-trapped charges and the interface-trapped charges, but also the fixed oxide charges resulting from structural defects and mobile charges generated by sodium (Na), lithium (Li), and potassium (K) ions. Stress-induced leakage current degrades data retention of non-volatile memories, causes problems during the writing and erasing of non-volatile memories and results in reliability issues.
Furthermore, the progress of science and technology has led to continual improvements in the performance of electronic systems and circuits. These improvements have fueled the increased demand for MOS transistors. In a MOS transistor, one of the most basic and critical requirements for proper operation is a stable threshold voltage. If the threshold voltage of a MOS transistor is unstable or out of spec, the turn-on and turn-off of the MOS transistor become abnormal and further affect the accuracy of the operation of an integrated circuit. Therefore, industry develops many methods to accurately judge the quality of oxide. Moreover, the same phenomenon can be found in capacitors and interconnection structures when adequate voltages are applied to one of the electrode plates and an upper layer interconnection, respectively.
Please refer to FIG. 3 and FIG. 4, FIG. 3 and FIG. 4 are resultant diagrams for judging the oxide quality by utilizing a C-V method according to the prior art. The C-V method, if taking an n-channel MOS device formed on a P-type substrate as an example, is to apply a swing time-dependent ramping voltage to the gate, from negative biased voltage to positive biased voltage. Due to the change of the voltage value, the surface of the P-type substrate underneath the gate varies through an accumulation mode, a depletion mode, and an inversion mode. The charge distribution is thus correspondingly changed. As shown in FIG. 3, the total capacitance of a MOS capacitor C is regarded as a series combination of the gate oxide layer capacitance (CO) and the semiconductor depletion-layer capacitance (Cj). Since C=dQ/dV, the change of charge distribution results in the change of the MOS capacitor C. By observing the typical C-V curve, the change of charge distribution under different modes is realized and the threshold voltage (VT) for MOS is found.
As shown in FIG. 4, the fixed oxide charges, the mobile charges, the oxide-trapped charges and the interface-trapped charges cause a C-V curve shift. The ideal C-V curve(a) affected by the fixed oxide charges, the mobile charges, and the oxide-trapped charges, is shifted toward left or right to become the C-V curve(b). Since the interface-trapped charges varies with the surface potential of the semiconductor (.S), the ideal C-V curve(a), affected by the interface-trapped charges, is not only shifted toward left or right but is also distorted to become the C-V curve(c).
FIG. 5 is a schematic diagram of the charge pumping method for judging the oxide quality according to the prior art. As shown in FIG. 5, if taking an NMOS device 34 formed on a P-type substrate 32 as an example, the charge pumping method is to tie a source 36 and a drain 38 of the NMOS 34 together first. The tied source 36 and the drain 38 are slightly reversed biased with voltage VR. A square-wave pulse train with a specific period is then applied between a gate 42 of the NMOS 34 and the P-type substrate 32. The square-wave pulse voltage is of sufficient amplitude for the channel 44, on a surface of the P-type substrate 32 underneath the gate 42, to be driven into an inversion mode at positive half cycle or an accumulation mode at negative half cycle. The interface traps (not shown) are continuously distributed through the band gap between the valence band and the conductive band.
When the square-wave pulse applied between the gate 42 and the P-type substrate 32 falls from a positive value to a negative value, electrons in the channel 44 during an inversion mode drift to both the source 36 and the drain 38. In addition, electrons captured by those interface traps near the conduction band are thermally emitted into the conduction band and also drift to the source 36 and the drain 38. Electrons captured by those interface traps do not have sufficient time to be thermally emitted and remain captured by the interface traps. Once the hole barrier is reduced, holes that flow to recombine with the electrons captured by those interface traps do not have sufficient time to be thermally emitted. When the square-wave pulse applied between the gate 42 and the P-type substrate 32 returns from the negative value to the positive value, holes captured by those interface traps near the valence band are thermally emitted into the valence band. Holes captured by those interface traps do not have sufficient time to be thermally emitted and remain captured on interface traps until recombining with electrons flowing in from the source 36 and the drain 38.
Hence, those electrons on interface traps within the energy interval .E recombine with the holes. If the electron density (electrons/cm2) flowing into the inversion layer from source/drain is QN/q, the electron density flowing back into the source/drain is only (QN/q−Dit.E) (Dit is interface trapped charge density, unit: cm−2.ev−1). Dit.E, the difference, recombine with the holes. Relatively speaking, Dit.E more holes flow into the P-type substrate 32 than leave, giving rise to the charge pumping current (Icp). A capacitor in parallel with the ammeter for measuring the charge pumping current averages the charge pumping current. Furthermore, if the period of the square-wave pulse is long enough so there is sufficient time for carriers to tunnel to the traps inside the oxide layer, the charge pumping method is utilized to measure the trapped charge density inside the oxide layer 46. The resultant charge-pumping-current versus gate-voltage (IcpVg) curve is shifted from a curve produced by a square-wave pulse of shorter duration, which measures only the interface trapped charge density.
Another prior art method to judge oxide quality is to measure the gate leakage current directly. A specific voltage value is applied to the gate of the non-volatile memory cell, and the gate leakage current is thereafter measured. If the gate leakage current is greater than a predetermined spec, the quality of the oxide layer is not acceptable. If the gate leakage current is less than the predetermined spec, the quality of the oxide layer is okay.
However, the prior art methods for judging the quality of the oxide layer all have limitations regardless of which method is used, the C-V method, the charge pumping method or to directly measure the gate leakage current. When compared with other methods, the C-V method requires a MOS capacitor with larger area, is feasible only when the charge quantity is larger than a specific value, and adds to measuring difficulties by using a more complicated equation. In addition, the C-V method cannot be applied to a production line because the wafer acceptance testing equipment cannot measure capacitance. The strength of the charge pumping method includes being applicable to small-geometry MOS devices and to obtain the direct measurement of the charge pumping current that is proportional to interface-trapped charge density. However, an AC pulse generator is required to supply the gate voltage and a single value for an average interface trapped charge density is obtained, rather than the energy distribution of the interface trapped charge density.
Though the method to directly measure the gate leakage current is quite simple, the information obtained is very limited. A cycling test is necessary if attempts are made to observe the change of the memory cell. In other words, the steps of writing, erasing, and measuring are repeated many times with consuming a large amount of time. In addition, the quality of the insulation layers in other devices or structures, such as capacitors, interconnection structures, etc., also need to be monitored. It is therefore very important to develop a new method to overcome the above mentioned problems and to be applied to the production line.